Phase shifted pwm resonant h-bridge supply !

Jagd.Panther

New member
View attachment 5682

how to build deadtime gardband for Q3,Q4 transient ?

else might be show as below spike will happen.
View attachment 5683

any input?
Hi cllow2020, the updated discrete driver schematic looks somewhat better. The easiest way is using high-/low-side driver with built-in interlock/dead-time generator. Other option is limit pulse width/duty cycle in MCU.

BTW there is a thread on GDT here, I posted there an example of a discrete driver with negative bias for higher dv/dt switching rates.
 

cllow2020

New member
Hi Jagd.Panther, thank you for guide me .:w)

View attachment 4_PSFB_discrete_drive.pdf
driver updated.

GDT pri coil current :
(15-1.6)/10 = 1.34A (di/dt impulse current)

SET Duty cycle 98% @100kHz
(1/100k)* 2% = 2usec.
whatever ZVT time; dead-time; delay time; ==> have to finished within 2usec.
GDT sec.coil current for each gate = 1.34/2= 0.67A (di/dt) or ~0.5A di/dt( someway estimated :D)

FET may not be fully saturated "ON" @2uS at 0.5A, gate charge current abit low.
maybe 5%@100Khz for total dead-time .
 

cllow2020

New member
Vo level shift

Vout level shift.jpg

if Vo =200v , output after level-shifted about 3.1v, it is capable to measure by MCU(3.3V) ADC
but,
if Vo =2V, Vo out ref will be extreme small, hard to measure by MCU.

is there a better measure method covered 0~200V Vo and capable to measure by MCU full range(0~3.3v)?
 
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2hartanto

New member
It's not to small. If you have 12 bit ADC you can measure 0 to 200V with 0.05V resolution.
 
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cllow2020

New member
Vo = 2V
after R36/(R31+R36) = 44.715mV
after level shift R27/R26 Gain = 14.756mV (Vo ref)
ADC resolution 3V3 / 1024 = 3.22mV (from 0~3.3)

most op-amp offset @100mV range, below its offset will not detected .
 
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2hartanto

New member
I'd like to say it is voltage divider. You don't need gain. Just resistor will work. I think 0-200V is wide range. It should be enough if you make 1V step
 

cllow2020

New member
good to have 3,22v @ Vo =200V.
if Vo = 2V, divider output 32.25mV , ADC resolution 3.2mV/step , than can measure 10 steps +/- 1

2V/610k = 3.23uA, this small current not good for ADC measurement.
 

cllow2020

New member
V0=2V, ADC measure at 1.805v ~ 2.195v (+/- 1 step) , 9.75% out
at 2V range can have nearly 10% out of accuracy. are this normal ?
 

cllow2020

New member
don't know , but i use 47K//230 having 4 step error, it must be below 47k (high site resister).
i use level-shift is to improve impedance and accuracy, but op-amp leading to other like offset error .
 
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