Simple Design Approach

destroyer x

Compulsive builder
You have presented a simple design..is this only a presentation?.... is you an expert to post this and to support people, to help people?...or you posted something just to be here doing some and know nothing about?

regards,

Carlos
 

Solcar

New member
Carlos, I have designed the USMPS circuit and can begin to explain how it works by describing how the oscillator section works. It is a classic hysteresis-type oscillator. When power is applied to the circuit, the gates (gate 1 and gate 2, for easier explanation) of the CD40106 (same as 74C14) are low. The inverted outputs of the gates are therefore at the chip power supply voltage level. Each feedback resistor then charges up the capacitance at each of the gates until the transition level of one of them is surpassed. That gate's output, say it was gate 1, then goes low, which feeds back to gate 2's input, forcing it low and therefore its output remains high. Which gate changed first depends on the slight tolerance differences between the gates on the particular IC chip.

Since gate 2 has a high output, its gate input voltage begins to rise as the capacitance there charges. When the voltage there reaches the trigger point (becomes high), its output swings low. The capacitor connecting gate 2's output to gate 1 then forces gate 1's input low and subsequently, its output high. Then the feedback resistor between gate 1's output and input begins to charge up the capacitance at its input. When it reaches the trigger point, its output swings low, forcing gate 2's input low and subsequently, output, high . The gate outputs then continue to take turns switching between high and low so long as the IC has sufficient power to function.

The oscillator can often work well enough using only one of the six sections of the hex Schmitt inverter IC, but I have used two in mutual a feedback configuration because that way, if the trigger points of the inputs of the chips are not centered at the middle level of the chip's power supply, the duty cycle will still stay low and high for equal time periods. That is important when the output to the transformer is push-pull as shown in the 12v voltage doubler circuit partly because the transformer isn't capacitor coupled to MOSFETs driving it. A capacitor would block net DC getting to the transformer windings.

Once the circuit is built on the simulator and in real life, it can be probed during operation. That way its operation can be seen as relatively simple. Much more of its operation is observable compared to the numerous PWM IC chips available (or not).

I have a lot of such circuits done in the free LTspice simulator at http://tech.groups.yahoo.com/group/switchmode/ in the files section. There, most of the circuits use the simpler, really super simple, oscillator topology that uses just one Schmitt trigger gate, one capacitor, and one resistor.

When I made the first USMPS circuit 7 or 8 years ago, I used the high quality National Semiconductor 74C14 ICs. Then, that three component oscillator produced square waves with much more even on and off times. Several years ago, National discontinued its logic gate manufacturing line.
 

Solcar

New member
Thanks Carlos. The explanation sounds much more complicated than the circuit really is. The main thing is that the two gate oscillator automatically compensates for less than ideal gates. In most circuits the super simple one gate oscillator is fine. Most non-USMPS (conventional) PWM circuits use a second frequency divider stage to obtain waveform symmetry.

The next section, the PWM circuit, passes each output of the oscillator stage through timing capacitors. The bias on the capacitors is adjusted to alter their charge rates. The two gates that follow then convert the resulting signals to square waves.

The current mode stage with the feedback transistor detects current through the sense resistor. When that current causes a rise in the voltage at the base, the transistor turns on more and raises its collector voltage. That rise in collector voltage speeds up the capacitor charge rate in the PWM stage, shortening the duty cycle.
 

ledo

New member
Sorry just can't put on GIF image. Why is that? Icon "Insert Image" request URL addrress, but I have image on my computer !?!?
 

Justicer

New member
Nice thread..... but it is stopped...why?

This one is a very interesting thread...i hope it continues.

regards,

Carlos
 

ledo

New member
Much time gone since I tryed but here it is. It is just another stile of sch drawing and you can see much more from schematics like that.



Hope this will work.
 
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