whats the best boost pfc feedback loop explanation you've seen?

J

JGalt

New member
Im teaching myself about boost pfc and while I've seen several datasheet/app note diagrams showing how the gain modulator/error feedback system is schematically, I've not yet seen a more intuitive explanation that perhaps has more diagrams showing how the feedback loop actually works to convert DC current demand at the output into a phase locked sinusoidal current at the input. I get that the input current waveforum must be:

-sinusoidal (easy to understand, otherwise its not PFC)
-in phase with the input voltage (easy to understand, otherwise its not PFC)
-proportional to the current being demanded by the output (easy to understand as a GOAL, but not so sure how its actually accomplished)

I'm imagining that the input current waveform basically just changes amplitude proportional to how much current is being demanded at the output. Therefore there is only ONE variable, and thats amplitude of the input current. Its always a sine wave, and its always phase locked to the input voltage. Is that right??

But how is that done? And is it on a cycle-by-cycle basis or can changes to it occur mid-cycle? How fast does it respond? Etc..

I'm guessing alot of those details are loop compensation, so I can shelve those questions for the moment.

What I need more clarification on is how the loop functions period. I seem to see a sine wave reference being generated by the input voltage. Then that times an output voltage signal creates a modulating signal to drive the switching fets PWM. But it still seems muddy. Maybe I just need to stare at those error amp block diagrams until it makes sense.

Hoping someone has seen a really good intuitive explanation of it.

The best I've yet seen is probably Unitrode 134, heres an excerpt

 
Last edited:
T

Triode

New member
You want it to act like a resistor, taking a current from the line proportional to the line voltage.

The reason it requires a complicated multiplier is so that we can adjust the current we're transferring. We have the signal Vvea, which represents how much current the system wants. We multiply that value by a scaled-down version of the half-sinusoidal input, which results in a half-sinusoidal control signal Imo. Then toggle the switch proportional to Imo, and the current you take from the line also looks like a half-sinusoid - voila, our system looks like a resistor to the AC line (albeit a variable resistor), and we have perfect power factor.
 
J

JGalt

New member
Triode said:
You want it to act like a resistor, taking a current from the line proportional to the line voltage.

The reason it requires a complicated multiplier is so that we can adjust the current we're transferring. We have the signal Vvea, which represents how much current the system wants. We multiply that value by a scaled-down version of the half-sinusoidal input, which results in a half-sinusoidal control signal Imo. Then toggle the switch proportional to Imo, and the current you take from the line also looks like a half-sinusoid - voila, our system looks like a resistor to the AC line (albeit a variable resistor), and we have perfect power factor.
Click to expand...

Thanks I guess that what I said was correct then, but it helps to hear someone elses interpretation of it, there are alot of moving parts here. Re-reading it what you say is perfectly clear in it now of course. Am I correct that what is not shown in that diagram is how the Imo signal is being utilized as far as inductor current mode? I.e. DCM/BCM/CCM? Or is that somehow intrinsic in how that particular feedback loop is laid out? Elsewhere in that same app note it does mention that the chip being discussed switches between CCM and DCM so I think that suggests that it happens inside the "white box" and not as part of figure 3's details. In other words the comparators or whatever that drive the switches to implement "average current control" are not shown in figure 3, and thats where the DCM/BCM/CCM action would be taking place.

What are the pros and cons of implementing the entire controller in this instance with an MCU? I would think some interesting compensation possibilities and other loop customizations would be possible, on the other hand it could just be pointlessly re-inventing the wheel considering how many SMPS IC's are out there and how heavily every possible improvement has been incorporated into them.
 
2

2rock

New member
The current mode of your PFC is highly dependable on the ripple current and the output power.
First the choice of the PFC IC determines the preferred current mode but as the output power decreases the PFC is not able to stay in continuous conduction mode and transits to discontinuous conduction mode. In the book "Switching Power Supplies A to Z" from Maniktala is a detailed explanation.
As the output voltage of a PFC is constant, the output current decreases with the output power.
The ripple current is defined as a percentage of the output current so that: delta I = r * Io
Maniktala derives a formula for the boost converter that shows how the inductivity L, output voltage Uo, switching frequency fsw, and the duty cycle D determine the current ripple r:
r = Vo / (Io * L * fsw) * D * (1-D)[SUP]2[/SUP]
When r = 2 the boost converter transits from CCM to DCM, so he rearranges the formula to calculate the minimum output current Io, so that the PFC works always in CCM. In a boost converter the most likely duty cycle for a transition between CCM and DCM is at D = 0.33.

I stumbled upon this knowledge after I already designed and built my CCM PFC, so now I have the problem, that my PFC is not working correctly at light loads because the IC works in DCM mode and Burst Mode instead of CCM.
 
J

JGalt

New member
2rock said:
The current mode of your PFC is highly dependable on the ripple current and the output power.
First the choice of the PFC IC determines the preferred current mode but as the output power decreases the PFC is not able to stay in continuous conduction mode and transits to discontinuous conduction mode. In the book "Switching Power Supplies A to Z" from Maniktala is a detailed explanation.
As the output voltage of a PFC is constant, the output current decreases with the output power.
The ripple current is defined as a percentage of the output current so that: delta I = r * Io
Maniktala derives a formula for the boost converter that shows how the inductivity L, output voltage Uo, switching frequency fsw, and the duty cycle D determine the current ripple r:
r = Vo / (Io * L * fsw) * D * (1-D)[SUP]2[/SUP]
When r = 2 the boost converter transits from CCM to DCM, so he rearranges the formula to calculate the minimum output current Io, so that the PFC works always in CCM. In a boost converter the most likely duty cycle for a transition between CCM and DCM is at D = 0.33.

I stumbled upon this knowledge after I already designed and built my CCM PFC, so now I have the problem, that my PFC is not working correctly at light loads because the IC works in DCM mode and Burst Mode instead of CCM.
Click to expand...

Good topic. So I'm probably going to need to understand why DCM is a natural consequence in boost pfc. Are the following correct:

-transition from CCM to DCM is _inevitable_ (?) in any boost converter (not just PFC) when the load becomes light enough to where its not consuming the minimum amount of current the boost converter can output (the reason there is a "minimum" is not clear to me, more below

-this is because as light loads/no load, as described by this IRF paper: http://www.irf.com/technical-info/whitepaper/pesc2005_controlofboostconverter.pdf

"First, if the boost converter is operated in the continuous–conduction
mode (CCM), there is a right half plane zero, which is
difficult to be stable. The discontinuous conduction mode is
desired for low power application. Second, at light load,
boost converter is difficult to regulate because PWM
controller typical has certain minimum on time and the on
time of switch at fixed frequency will keep pumping energy
to output and it will cause over voltage at very light load or
no load condition."


The second half of that (in bold) seems a little ambiguous. Why does a controller typically have a minimum on time? Simply as a result of how the ramps/comparators for PWM generation operate? Isn't that kind of a fake artifact that could be eliminated with a slightly more sophisticated controller?

And is it "difficult to regulate" purely because of that, or because of some other reason?

The idea that energy keeps getting pumped to the output because of the "minimum switch on time" makes sense, but the reasons for that minimum on time dont yet. And its not really made clear why DCM is part of this. Of course I suppose if there is some non zero current through the inductor, that current makes it to the load, and if the load isn't consuming it, the output voltage will rise. But why would this transition occur at 33% as you mentioned? That seems awfully high still to have problems regulating.

So I guess thats why I should keep looking for a better explanation. But its a conversation starter hopefully!

EDIT: Okay so thinking a bit more it makes a little more sense why DCM would occur at light loads. However, where "light load is" as far as inductor duty cycle is alot more complicated and should have to do with many design factors I think.

So if we imagine, in a boost pfc, operating in CCM, the inductor current is a sawtooth that follows the sine wave voltage input.

As load gets lighter and lighter, sawtooth bottom tips approach zero current. When they touch, now its DCM (or BrCM etc..).

When this moment happens as far as duty cycle/load seems to me is related to inductor ripple current design and that is a derivative of many other design choices yes? Would be interesting to see where the 33% comes from in the book you mentioned. But maybe you spelled it out perfectly and its all there and I just need to stare at it, from your post:

2rock:

"In the book "Switching Power Supplies A to Z" from Maniktala is a detailed explanation.
As the output voltage of a PFC is constant, the output current decreases with the output power.
The ripple current is defined as a percentage of the output current so that: delta I = r * Io
Maniktala derives a formula for the boost converter that shows how the inductivity L, output voltage Uo, switching frequency fsw, and the duty cycle D determine the current ripple r:
r = Vo / (Io * L * fsw) * D * (1-D)2
When r = 2 the boost converter transits from CCM to DCM, so he rearranges the formula to calculate the minimum output current Io, so that the PFC works always in CCM. In a boost converter the most likely duty cycle for a transition between CCM and DCM is at D = 0.33.
"
 
Last edited:
J

JGalt

New member
This excerpt from "Power Switching Converters" 2nd Ed. by Ang and Oliva (quickly becoming my favorite) has some juicy tidbits on CCM/DCM in Boost topology.




 
2

2rock

New member
JGalt said:
Good topic. So I'm probably going to need to understand why DCM is a natural consequence in boost pfc. Are the following correct:

-transition from CCM to DCM is _inevitable_ (?) in any boost converter (not just PFC) when the load becomes light enough to where its not consuming the minimum amount of current the boost converter can output (the reason there is a "minimum" is not clear to me, more below
Click to expand...
Yes, it es inevitable in any boost converter but even in buck and buck-boost topologies there is a transition from CCM to DCM and vice versa.
Maniktala writes, that three things cause the transition from CCM to DCM: decreasing the lead, decreasing the inductance (e.i. using a small inductor), increasing the input voltage.

-this is because as light loads/no load, as described by this IRF paper: http://www.irf.com/technical-info/whitepaper/pesc2005_controlofboostconverter.pdf

"First, if the boost converter is operated in the continuous–conduction
mode (CCM), there is a right half plane zero, which is
difficult to be stable. The discontinuous conduction mode is
desired for low power application. Second, at light load,
boost converter is difficult to regulate because PWM
controller typical has certain minimum on time and the on
time of switch at fixed frequency will keep pumping energy
to output and it will cause over voltage at very light load or
no load condition."


The second half of that (in bold) seems a little ambiguous. Why does a controller typically have a minimum on time? Simply as a result of how the ramps/comparators for PWM generation operate? Isn't that kind of a fake artifact that could be eliminated with a slightly more sophisticated controller?
Click to expand...
There are also controllers with fixed off time so designers can take advantage of that. But I can't say to what effect.

And is it "difficult to regulate" purely because of that, or because of some other reason?

The idea that energy keeps getting pumped to the output because of the "minimum switch on time" makes sense, but the reasons for that minimum on time dont yet. And its not really made clear why DCM is part of this. Of course I suppose if there is some non zero current through the inductor, that current makes it to the load, and if the load isn't consuming it, the output voltage will rise. But why would this transition occur at 33% as you mentioned? That seems awfully high still to have problems regulating.
Click to expand...
Maniktala shows different graphs for Buck, Buck-Boost and Boost converters and the ripple current ratio r peaks at D = 0.33. In the other topologies the current ripple ration r is just falling with increasing duty cycle.

EDIT: Okay so thinking a bit more it makes a little more sense why DCM would occur at light loads. However, where "light load is" as far as inductor duty cycle is alot more complicated and should have to do with many design factors I think.
Click to expand...
As far as my research goes by comparing different controllers (DCM, CCM, FCCrM, Interleaved, Bridgeless) from different IC manufacturers and reference designs, the light load condition begins with less than 20 % output power. Interleaved and bridgeless designs seem to go as far as 10 % output power before the light load condition occurs and power factor drops as well as efficiency. That is the reason many PFC ICs use burst mode at light load but it doesn't help to avoid the drop in power factor.

I suggest reading the Power Factor Correction Handbook from ON Semi http://www.onsemi.com/pub_link/Collateral/HBD853-D.PDF for a better comparison between DCM, CCM and the other topologies.
 
J

JGalt

New member
2rock said:
Yes, it es inevitable in any boost converter but even in buck and buck-boost topologies there is a transition from CCM to DCM and vice versa.
Maniktala writes, that three things cause the transition from CCM to DCM: decreasing the lead, decreasing the inductance (e.i. using a small inductor), increasing the input voltage.


There are also controllers with fixed off time so designers can take advantage of that. But I can't say to what effect.


Maniktala shows different graphs for Buck, Buck-Boost and Boost converters and the ripple current ratio r peaks at D = 0.33. In the other topologies the current ripple ration r is just falling with increasing duty cycle.


As far as my research goes by comparing different controllers (DCM, CCM, FCCrM, Interleaved, Bridgeless) from different IC manufacturers and reference designs, the light load condition begins with less than 20 % output power. Interleaved and bridgeless designs seem to go as far as 10 % output power before the light load condition occurs and power factor drops as well as efficiency. That is the reason many PFC ICs use burst mode at light load but it doesn't help to avoid the drop in power factor.

I suggest reading the Power Factor Correction Handbook from ON Semi http://www.onsemi.com/pub_link/Collateral/HBD853-D.PDF for a better comparison between DCM, CCM and the other topologies.
Click to expand...

I'll add that pdf to my ever growing library of SMPS docs to read, thank you.

So what is your strategy now that you know of the DCM problem with your current design? Are you going to basically start completely over or can you resolve it somehow?

In your design, does the DCM at least occur exactly when you would expect it to as far as the above equations?
 
2

2rock

New member
Due to time constraints I'll stick to this design and hope to improve my design by better PCB layout. But there is a need for a complete redesign in the future including the downstream DC-DC-Converter. There are two similar reference designs from Fairchild and TI that appear to be a good starting point.

Fairchild RD-573 https://www.fairchildsemi.com/reference-designs/RD-573.pdf

TI slou293c http://www.ti.com/lit/ug/slou293c/slou293c.pdf

PS: Yes the transition happened as expected (ignoring the efficiency of the converters and amplifiers). As I designed a 300 W PFC with r = 0.4 the PFC entered CCM when the downstream amplifier delivered 64W into 4R load, equaling 20% output power.
 
Last edited:
J

JGalt

New member
2rock said:
Due to time constraints I'll stick to this design and hope to improve my design by better PCB layout. But there is a need for a complete redesign in the future including the downstream DC-DC-Converter. There are two similar reference designs from Fairchild and TI that appear to be a good starting point.

Fairchild RD-573 https://www.fairchildsemi.com/reference-designs/RD-573.pdf

TI slou293c http://www.ti.com/lit/ug/slou293c/slou293c.pdf

PS: Yes the transition happened as expected (ignoring the efficiency of the converters and amplifiers). As I designed a 300 W PFC with r = 0.4 the PFC entered CCM when the downstream amplifier delivered 64W into 4R load, equaling 20% output power.
Click to expand...

I would consider your design a major success considering it is working as the equations predict! Do you have a thread detailing this project?
 
You must log in or register to reply here.
Top